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Freescale Semiconductor
Document Number: MPC8250EC Rev. 1, 03/2005
MPC8250 Hardware Specifications
This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC8250 PowerQUICC IITM communications processor. The following topics are addressed: The MPC8250 is available in two packages--the standard ZU package (480 TBGA) and an alternate VR package (516 PBGA)--as described in Section 4, "Pinout," and Section 5, "Package Description." For more information on VR packages, contact your Freescale sales office. Note that throughout this document references to the MPC8250 are inclusive of its VR version unless otherwise specified.
1. 2. 3. 4. 5. 6. 7.
Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Electrical and Thermal Characteristics . . . . . . . . . . . . 6 Clock Configuration Modes . . . . . . . . . . . . . . . . . . . 20 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 55 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 58 Document Revision History . . . . . . . . . . . . . . . . . . . 58
This document contains information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2003, 2005. All rights reserved.
Features
Figure 1 shows the block diagram for the MPC8250.
16 Kbytes I-Cache I-MMU G2 Core System Interface Unit (SIU) 16 Kbytes D-Cache D-MMU Bus Interface Unit 60x-to-PCI Bridge 60x-to-Local Bridge Memory Controller Timers Parallel I/O Baud Rate Generators 32-bit RISC Microcontroller and Program ROM 4 Virtual IDMAs System Functions Interrupt Controller 32 Kbytes Dual-Port RAM Serial DMAs Clock Counter 60x Bus
PCI Bus
32 bits, up to 66 MHz or
Local Bus
32 bits, up to 66 MHz
Communication Processor Module (CPM)
MCC2
FCC1
FCC2
FCC3
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
SPI
I2C
Time Slot Assigner Serial Interface
4 TDM Ports
3 MII Ports
Non-Multiplexed I/O
Figure 1. MPC8250 Block Diagram
1
Features
The major features of the MPC8250 are as follows: * Footprint-compatible with the MPC8260 * Dual-issue integer core -- A core version of the EC603e microprocessor -- System core microprocessor supporting frequencies of 150-200 MHz -- Separate 16-Kbyte data and instruction caches: - Four-way set associative - Physically addressed - LRU replacement algorithm -- PowerPC architecture-compliant memory management unit (MMU) -- Common on-chip processor (COP) test interface -- High-performance (4.4-5.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at 200 MHz)
MPC8250 Hardware Specifications, Rev. 1 2 Freescale Semiconductor
Features
* *
*
*
*
*
*
-- Supports bus snooping for data cache coherency -- Floating-point unit (FPU) Separate power supply for internal logic (1.8 V) and for I/O (3.3V) Separate PLLs for G2 core and for the CPM -- G2 core and CPM can run at different frequencies for power/performance optimization -- Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios -- Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios 64-bit data and 32-bit address 60x bus -- Bus supports multiple master designs -- Supports single- and four-beat burst transfers -- 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller -- Supports data parity or ECC and address parity 32-bit data and 18-bit address local bus -- Single-master bus, supports external slaves -- Eight-beat burst transfers -- 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller 60x-to-PCI bridge -- Programmable host bridge and agent -- 32-bit data bus, 66 MHz, 3.3 V -- Synchronous and asynchronous 60x and PCI clock modes -- All internal address space available to external PCI host -- DMA for memory block transfers -- PCI-to-60x address remapping System interface unit (SIU) -- Clock synthesizer -- Reset controller -- Real-time clock (RTC) register -- Periodic interrupt timer -- Hardware bus monitor and software watchdog timer -- IEEE 1149.1 JTAG test access port Twelve-bank memory controller -- Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other userdefinable peripherals -- Byte write enables and selectable parity generation -- 32-bit address decodes with programmable bank size -- Three user programmable machines, general-purpose chip-select machine, and page-mode pipeline SDRAM machine -- Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)
MPC8250 Hardware Specifications, Rev. 1
Freescale Semiconductor
3
Features
* *
-- Dedicated interface logic for SDRAM CPU core can be disabled and the device can be used in slave mode to an external core Communications processor module (CPM) -- Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for communications protocols -- Interfaces to G2 core through on-chip 32-Kbyte dual-port RAM and DMA controller -- Serial DMA channels for receive and transmit on all serial channels -- Parallel I/O registers with open-drain and interrupt capability -- Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers -- Three fast communications controllers supporting the following protocols: - 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent interface (MII) - Transparent - HDLC--Up to T3 rates (clear channel) -- One multichannel controller (MCC2) - Handles 128 serial, full-duplex, 64-Kbps data channels. The MCC can be split into four subgroups of 32 channels each. - Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces up to four TDM interfaces per MCC -- Four serial communications controllers (SCCs) identical to those on the MPC860, supporting the digital portions of the following protocols: - Ethernet/IEEE 802.3 CDMA/CS - HDLC/SDLC and HDLC bus - Universal asynchronous receiver transmitter (UART) - Synchronous UART - Binary synchronous (BISYNC) communications - Transparent -- Two serial management controllers (SMCs), identical to those of the MPC860 - Provide management for BRI devices as general circuit interface (GCI) controllers in timedivision-multiplexed (TDM) channels - Transparent - UART (low-speed operation) -- One serial peripheral interface identical to the MPC860 SPI -- One inter-integrated circuit (I2C) controller (identical to the MPC860 I2C controller) - Microwire compatible - Multiple-master, single-master, and slave modes -- Up to four TDM interfaces - Supports one group of four TDM channels
MPC8250 Hardware Specifications, Rev. 1 4 Freescale Semiconductor
Features
*
2,048 bytes of SI RAM Bit or byte resolution Independent transmit and receive routing, frame synchronization Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN primary rate, Freescale interchip digital link (IDL), general circuit interface (GCI), and user-defined TDM serial interfaces -- Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs, SCCs, SMCs, and serial channels -- Four independent 16-bit timers that can be interconnected as two 32-bit timers PCI bridge -- PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz -- On-chip arbitration -- Support for PCI to 60x memory and 60x memory to PCI streaming -- PCI Host Bridge or Peripheral capabilities -- Includes 4 DMA channels for the following transfers: - PCI-to-60x to 60x-to-PCI - 60x-to-PCI to PCI-to-60x - PCI-to-60x to PCI-to-60x - 60x-to-PCI to 60x-to-PCI -- Includes all of the configuration registers (which are automatically loaded from the EPROM and used to configure the MPC8265A) required by the PCI standard as well as message and doorbell registers -- Supports the I2O standard -- Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0 August 3, 1998) -- Support for 66 MHz, 3.3 V specification -- 60x-PCI bus core logic which uses a buffer pool to allocate buffers for each port -- Makes use of the local bus signals, so there is no need for additional pins
- - - -
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 5
Electrical and Thermal Characteristics
2
2.1
Electrical and Thermal Characteristics
DC Electrical Characteristics
This section provides AC and DC electrical specifications and thermal characteristics for the MPC8250.
This section describes the DC electrical characteristics for the MPC8250. Table 1 shows the maximum electrical ratings.
Table 1. Absolute Maximum Ratings 1
Rating Core supply voltage 2 PLL supply I/O supply voltage2 Symbol VDD VCCSYN VDDH VIN Tj TSTG Value -0.3 - 2.5 -0.3 - 2.5 -0.3 - 4.0 GND(-0.3) - 3.6 120 (-55) - (+150) Unit V V V V C C
voltage 3
Input voltage 4 Junction temperature Storage temperature range
1
Absolute maximum ratings are stress ratings only; functional operation (see Table 2) at the maximums is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage. 2 Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset. 3 Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec. VDDH should not exceed VDD/VCCSYN by more than 2.5 V during normal operation. 4 Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.
Table 2 lists recommended operational voltage conditions.
Table 2. Recommended Operating Conditions 1
Rating Core supply voltage PLL supply voltage I/O supply voltage Input voltage Junction temperature (maximum) Ambient temperature
1 2 3 4 5
Symbol VDD VCCSYN VDDH VIN Tj TA 1.7 - 1.9 2 1.7 - 1.92
Value 1.7-2.1 3 1.7-2.13 3.135 - 3.465 GND (-0.3) - 3.465 105 5 0-705 1.9 -2.2 4 1.9-2.24
Unit V V V V C C
Caution: These are the recommended and tested operating conditions. Proper device operating outside of these conditions is not guaranteed. CPU frequency less than or equal to 200 MHz. CPU frequency greater than 200 MHz but less than 233 MHz. CPU frequency greater than or equal to 233 MHz. Note that for extended temperature parts the range is (-40)T - 105Tj.
A
MPC8250 Hardware Specifications, Rev. 1 6 Freescale Semiconductor
Electrical and Thermal Characteristics
NOTE: Core, PLL, and I/O Supply Voltages
VDDH, VCCSYN, and VDD must track each other and both must vary in the same direction--in the positive direction (+5% and +0.1 Vdc) or in the negative direction (-5% and -0.1 Vdc). This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (either GND or VCC). Figure 2 shows the undershoot and overshoot voltage of the 60x and local bus memory interface of the MPC8280. Note that in PCI mode the I/O interface is different.
4V GVDD + 5% GVDD
VIH
VIL
GND GND - 0.3 V GND - 1.0 V Not to exceed 10% of tSDRAM_CLK
Figure 2. Overshoot/Undershoot Voltage
Table 3 shows DC electrical characteristics.
Table 3. DC Electrical Characteristics 1
Characteristic Input high voltage, all inputs except CLKIN Input low voltage CLKIN input high voltage CLKIN input low voltage Input leakage current, VIN = VDDH
2 2
Symbol VIH VIL VIHC VILC IIN IOZ IL IH VOH
Min 2.0 GND 2.4 GND -- -- -- -- 2.4
Max 3.465 0.8 3.465 0.4 10 10 1 1 --
Unit V V V V A A A A V
Hi-Z (off state) leakage current, VIN = VDDH Signal low input current, VIL = 0.8 V Signal high input current, VIH = 2.0 V Output high voltage, IOH = -2 mA
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 7
Electrical and Thermal Characteristics
Table 3. DC Electrical Characteristics 1 (continued)
Characteristic IOL = 7.0mA BR BG ABB/IRQ2 TS A[0-31] TT[0-4] TBST TSIZE[0-3] AACK ARTRY DBG DBB/IRQ3 D[0-63] DP(0)/RSRV/EXT_BR2 DP(1)/IRQ1/EXT_BG2 DP(2)/TLBISYNC/IRQ2/EXT_DBG2 DP(3)/IRQ3/EXT_BR3/CKSTP_OUT DP(4)/IRQ4/EXT_BG3/CORE_SREST DP(5)/TBEN/IRQ5/EXT_DBG3 DP(6)/CSE(0)/IRQ6 DP(7)/CSE(1)/IRQ7 PSDVAL TA TEA GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 L2_HIT/IRQ4 CPU_BG/BADDR31/IRQ5 CPU_DBG CPU_BR IRQ0/NMI_OUT IRQ7/INT_OUT/APE PORESET HRESET SRESET RSTCONF QREQ Symbol VOL Min -- Max 0.4 Unit V
MPC8250 Hardware Specifications, Rev. 1 8 Freescale Semiconductor
Electrical and Thermal Characteristics
Table 3. DC Electrical Characteristics 1 (continued)
Characteristic IOL = 5.3mA CS[0-9] CS(10)/BCTL1 CS(11)/AP(0) BADDR[27-28] ALE BCTL0 PWE(0:7)/PSDDQM(0:7)/PBS(0:7) PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 LWE[0-3]LSDDQM[0:3]/LBS[0-3]/PCI_CFG[0-3 LSDA10/LGPL0/PCI_MODCKH0 LSDWE/LGPL1/PCI_MODCKH1 LOE/LSDRAS/LGPL2/PCI_MODCKH2 LSDCAS/LGPL3/PCI_MODCKH3 LGTA/LUPMWAIT/LGPL4/LPBS LSDAMUX/LGPL5/PCI_MODCK LWR MODCK1/AP(1)/TC(0)/BNKSEL(0) MODCK2/AP(2)/TC(1)/BNKSEL(1) MODCK3/AP(3)/TC(2)/BNKSEL(2) IOL = 3.2mA L_A14/PAR L_A15/FRAME/SMI L_A16/TRDY L_A17/IRDY/CKSTP_OUT L_A18/STOP L_A19/DEVSEL L_A20/IDSEL L_A21/PERR L_A22/SERR L_A23/REQ0 L_A24/REQ1/HSEJSW L_A25/GNT0 L_A26/GNT1/HSLED L_A27/GNT2/HSENUM L_A28/RST/CORE_SRESET L_A29/INTA L_A30/REQ2 L_A31 LCL_D(0-31)/AD(0-31) LCL_DP(0-3)/C/BE(0-3) PA[0-31] PB[4-31] PC[0-31] PD[4-31] TDO Symbol VOL Min -- Max 0.4 Unit V
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 9
Electrical and Thermal Characteristics
1
The default configuration of the CPM pins (PA[0-31], PB[4-31], PC[0-31], PD[4-31]) is input. To prevent excessive DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs. 2 The leakage current is measured for nominal VDD, VCCSYN, and VDD.
2.2
Thermal Characteristics
Table 4. Thermal Characteristics
Value Characteristic Symbol 480 TBGA (ZU package) 13 10 JA 11 8 JB JC 4 1.1 516 PBGA (VR package) 24 18 16 13 8 6 C/W C/W C/W Unit Air Flow
Table 4 describes thermal characteristics.
Junction to ambient-- single-layer board 1 Junction to ambient-- four-layer board Junction to board 2
Natural convection 1 m/s Natural convection 1 m/s -- --
Junction to case 3
1 2
Assumes no thermal vias Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 3 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
2.3
Power Considerations
(1)
The average chip-junction temperature, TJ, in C can be obtained from the following: TJ = TA + (PD x JA) where
TA = ambient temperature C
JA = package thermal resistance, junction to ambient, C/W PD = PINT + PI/O
PINT = IDD x VDD Watts (chip internal power) PI/O = power dissipation on input and output pins (determined by user)
For most applications PI/O < 0.3 x PINT. If PI/O is neglected, an approximate relationship between PD and TJ is the following:
PD = K/(T J + 273 C) (2)
Solving equations (1) and (2) for K gives: K = PD x (TA + 273 C) + JA x PD2
(3)
MPC8250 Hardware Specifications, Rev. 1 10 Freescale Semiconductor
Electrical and Thermal Characteristics
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA.
2.3.1
Layout Practices
Each VCC pin should be provided with a low-impedance path to the board's power supply. Each ground pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on chip. The VCC power supply should be bypassed to ground using at least four 0.1 F by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VCC and ground should be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND planes. All output pins on the MPC8250 have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized in order to minimize overdamped conditions and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the VCC and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. Table 5 provides preliminary, estimated power dissipation for various configurations. Note that suitable thermal management is required for conditions above PD = 3W (when the ambient temperature is 70 C or greater) to ensure the junction temperature does not exceed the maximum specified value. Also note that the I/O power should be included when determining whether to use a heat sink.
Table 5. Estimated Power Dissipation for Various Configurations 1
PINT(W) 2 Bus (MHz) CPM Core CPU Multiplier Multiplier CPM (MHz) CPU (MHz) Vddl 1.8 Volts Nominal 66.66 66.66 66.66 66.66 83.33 83.33 83.33
1 2
Vddl 2.0 Volts Nominal 1.8 1.9 2.3 2.4 2.2 2.2 2.4 Maximum 2.3 2.3 2.9 3.1 2.8 2.8 3.1
Maximum 2 2.1 -- -- -- -- --
2 2.5 3 3 2 2 2.5
3 3 4 4.5 3 3 3.5
133 166 200 200 166 166 208
200 200 266 300 250 250 291
1.2 1.3 -- -- -- -- --
Test temperature = room temperature (25 C) PINT = IDD x V DD Watts
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 11
Electrical and Thermal Characteristics
2.4
AC Electrical Characteristics
The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and inputs for the 66 MHz MPC8250 device. Note that AC timings are based on a 50-pf load. Typical output buffer impedances are shown in Table 6.
Table 6. Output Buffer Impedances 1
Output Buffers 60x bus Local bus Memory controller Parallel I/O PCI
1
Typical Impedance () 40 40 40 46 25
These are typical values at 65 C. The impedance may vary by 25% with process and temperature.
Table 7 lists CPM output characteristics.
Table 7. AC Characteristics for CPM Outputs 1
Spec Number Characteristic Max sp36a sp36b sp40 sp38a sp38b sp42 sp42a
1
Max Delay (ns)
Min Delay (ns)
Min sp37a sp37b sp41 sp39a sp39b sp43 sp43a FCC outputs--internal clock (NMSI) FCC outputs--external clock (NMSI) TDM outputs/SI SCC/SMC/SPI/I2C outputs--internal clock (NMSI) Ex_SCC/SMC/SPI/I2C outputs--external clock (NMSI) TIMER/IDMA outputs PIO outputs
66 MHz 83 MHz 66 MHz 83 MHz 6 14 25 19 19 14 14 5.5 12 16 16 16 11 11 1 2 5 1 2 1 0.5 1 1 4 0.5 1 0.5 0.5
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin.
Table 8 lists CPM input characteristics.
Table 8. AC Characteristics for CPM Inputs 1
Spec Number Characteristic Max sp16a sp16b Min sp17a sp17b FCC inputs--internal clock (NMSI) FCC inputs--external clock (NMSI) 66 MHz 83 MHz 66 MHz 83 MHz 10 3 8 2.5 0 3 0 2 Setup (ns) Hold (ns)
MPC8250 Hardware Specifications, Rev. 1 12 Freescale Semiconductor
Electrical and Thermal Characteristics
Table 8. AC Characteristics for CPM Inputs 1
Spec Number Characteristic Max sp20 sp18a sp18b sp22
1
Setup (ns)
Hold (ns)
Min sp21 sp19a sp19b sp23 TDM inputs/SI SCC/SMC/SPI/I2C inputs--internal clock (NMSI) SCC/SMC/SPI/I2C inputs--external clock (NMSI) PIO/TIMER/IDMA inputs
66 MHz 83 MHz 66 MHz 83 MHz 15 20 5 10 12 16 4 8 12 0 5 3 10 0 4 3
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin.
Note that although the specifications generally reference the rising edge of the clock, the following AC timing diagrams also apply when the falling edge is the active edge.
Figure 3 shows the FCC external clock.
Serial ClKin sp17b sp16b FCC input signals sp36b/sp37b FCC output signals
Note: When GFMR[TCI] = 0
sp36b/sp37b FCC output signals
Note: When GFMR[TCI] = 1
Figure 3. FCC External Clock Diagram
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 13
Electrical and Thermal Characteristics
Figure 4 shows the FCC internal clock.
BRG_OUT sp17a sp16a FCC input signals sp36a/sp37a FCC output signals
Note: When GFMR.TCI = 0
sp36a/sp37a
FCC output signals
Note: When GFMR.TCI = 1
Figure 4. FCC Internal Clock Diagram
Figure 5 shows the SCC/SMC/SPI/I2C external clock.
Serial CLKin sp18b SCC/SMC/SPI/I2C input signals
(See note.)
sp19b
sp38b/sp39b SCC/SMC/SPI/I2C output signals
(See note.)
Note: There are four possible timing conditions for SCC and SPI: 1. Input sampled on the rising edge and output driven on the rising edge (shown). 2. Input sampled on the rising edge and output driven on the falling edge. 3. Input sampled on the falling edge and output driven on the falling edge. 4. Input sampled on the falling edge and output driven on the rising edge.
Figure 5. SCC/SMC/SPI/I2C External Clock Diagram
MPC8250 Hardware Specifications, Rev. 1 14 Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 6 shows the SCC/SMC/SPI/I2C internal clock.
BRG_OUT sp18a SCC/SMC/SPI/I2C input signals
(See note.)
sp19a
sp38a/sp39a SCC/SMC/SPI/I2C output signals
(See note.)
Note: There are four possible timing conditions for SCC and SPI: 1. Input sampled on the rising edge and output driven on the rising edge (shown). 2. Input sampled on the rising edge and output driven on the falling edge. 3. Input sampled on the falling edge and output driven on the falling edge. 4. Input sampled on the falling edge and output driven on the rising edge.
Figure 6. SCC/SMC/SPI/I2C Internal Clock Diagram
Figure 7 shows TDM input and output signals.
Serial CLKin sp20 TDM input signals sp40/sp41 TDM output signals Note: There are four possible TDM timing conditions: 1. Input sampled on the rising edge and output driven on the rising edge (shown). 2. Input sampled on the rising edge and output driven on the falling edge. 3. Input sampled on the falling edge and output driven on the falling edge. 4. Input sampled on the falling edge and output driven on the rising edge. sp21
Figure 7. TDM Signal Diagram
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 15
Electrical and Thermal Characteristics
Figure 8 shows PIO, timer, and DMA signals.
Sys clk
sp23 sp22 PIO/IDMA/TIMER[TGATE assertion] input signals
(See note)
sp23 sp22
TIMER input signal [TGATE deassertion]
(See note)
sp42/sp43 IDMA output signals sp42/sp43 sp42a/sp43a TIMER(sp42/43)/ PIO(sp42a/sp43a) output signals Note: TGATE is asserted on the rising edge of the clock; it is deasserted on the falling edge.
Figure 8. PIO, Timer, and DMA Signal Diagram
Table 9 lists SIU input characteristics.
Table 9. AC Characteristics for SIU Inputs 1
Spec Number Characteristic Max sp11 sp12 sp13 sp14 sp15
1
Setup (ns)
Hold (ns)
Min sp10 sp10 sp10 sp10 sp10 AACK/ARTRY/TA/TS/TEA/DBG/BG/BR Data bus in normal mode Data bus in ECC and PARITY modes DP pins All other pins
66 MHz 83 MHz 66 MHz 83 MHz 6 5 8 7 5 5 4 6 6 4 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin.
MPC8250 Hardware Specifications, Rev. 1 16 Freescale Semiconductor
Electrical and Thermal Characteristics
Table 10 lists SIU output characteristics.
Table 10. AC Characteristics for SIU Outputs 1
Spec Number Characteristic Max sp31 sp32 sp33a sp33b sp34 sp35
1
Max Delay (ns)
Min Delay (ns)
Min sp30 sp30 sp30 sp30 sp30 sp30 PSDVAL/TEA/TA ADD/ADD_atr./BADDR/CI/GBL/WT Data bus DP Memory controller signals/ALE All other signals
66 MHz 83 MHz 66 MHz 83 MHz 7 8 6.5 8 6 6 6 6.5 6.5 7 5 5.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin.
NOTE
Activating data pipelining (setting BRx[DR] in the memory controller) improves the AC timing. When data pipelining is activated, sp12 can be used for data bus setup even when ECC or PARITY are used. Also, sp33a can be used as the AC specification for DP signals.
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 17
Electrical and Thermal Characteristics
Figure 9 shows the interaction of several bus signals.
CLKin sp11 AACK/ARTRY/TA/TS/TEA/ DBG/BG/BR input signals sp12 DATA bus normal mode input signal sp15 All other input signals sp31 PSDVAL/TEA/TA output signals sp32 ADD/ADD_atr/BADDR/CI/ GBL/WT output signals sp33a DATA bus output signals sp30 sp30 sp10 sp10 sp10
sp30
sp35
sp30
All other output signals
Figure 9. Bus Signals
Figure 10 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).
CLKin sp10 sp13 DATA bus, ECC, and PARITY mode input signals
sp10 sp14 DP mode input signal
sp33b/sp30 DP mode output signal
Figure 10. Parity Mode Diagram
MPC8250 Hardware Specifications, Rev. 1 18 Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 11 shows signal behavior in MEMC mode.
CLKin
V_CLK
Memory controller signals
sp34/sp30
Figure 11. MEMC Mode Diagram NOTE
Generally, all MPC8250 bus and system output signals are driven from the rising edge of the input clock (CLKin). Memory controller signals, however, trigger on four points within a CLKin cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge, and T3 at the falling edge, of CLKin. However, the spacing of T2 and T4 depends on the PLL clock ratio selected, as shown in Table 11.
Table 11. Tick Spacing for Memory Controller Signals
Tick Spacing (T1 Occurs at the Rising Edge of CLKin) PLL Clock Ratio T2 1:2, 1:3, 1:4, 1:5, 1:6 1:2.5 1:3.5 1/4 CLKin 3/10 CLKin 4/14 CLKin T3 1/2 CLKin 1/2 CLKin 1/2 CLKin T4 3/4 CLKin 8/10 CLKin 11/14 CLKin
Figure 12 is a graphical representation of Table 11.
CLKin T1 T2 T3 T4 for 1:2, 1:3, 1:4, 1:5, 1:6
CLKin T1 T2 T3 T4
for 1:2.5
CLKin T1 T2 T3 T4
for 1:3.5
Figure 12. Internal Tick Spacing for Memory Controller Signals
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 19
Clock Configuration Modes
NOTE
The UPM machine outputs change on the internal tick determined by the memory controller programming; the AC specifications are relative to the internal tick. Note that SDRAM and GPCM machine outputs change on CLKin's rising edge.
3
Clock Configuration Modes
The MPC8250 has three clocking modes: local, PCI host, and PCI agent. The clocking mode is set according to three input pins--PCI_MODE, PCI_CFG[0], PCI_MODCK--as shown in Table 12.
Table 12. MPC8250 Clocking Modes
Pins PCI_MODE 1 0 0 0 0
1
PCI_CFG[0] PCI_MODCK 1 -- 0 0 1 1 -- 0 1 0 1
Clocking Mode Local bus PCI host
PCI Clock Frequency Range (MHZ) -- 50-66 25-50 50-66
Reference Table 13 and Table 14 Table 15 and Table 16
PCI agent
25-50
Table 17 and Table 18
Determines PCI clock frequency range. Refer to Section 3.2, "PCI Mode."
In each clocking mode, the configuration of bus, core, PCI, and CPM frequencies is determined by seven bits during the power-up reset--three hardware configuration pins (MODCK[1-3]) and four bits from hardware configuration word[28-31] (MODCK_H). Both the PLLs and the dividers are set according to the selected MPC8250 clock operation mode as described in the following sections.
NOTE
Clock configurations change only after POR is asserted.
3.1
Local Bus Mode
Table 13 shows the eight basic clock configurations for the MPC8250. Another 49 configurations are available by using the configuration pin (RSTCONF) and driving four pins on the data bus.
Table 13. Clock Default Configurations
MODCK[1-3] 000 001 010 011 Input Clock Frequency 33 MHz 33 MHz 33 MHz 33 MHz CPM Multiplication Factor 3 3 4 4 CPM Frequency 100 MHz 100 MHz 133 MHz 133 MHz Core Multiplication Factor 4 5 4 5 Core Frequency 133 MHz 166 MHz 133 MHz 166 MHz
MPC8250 Hardware Specifications, Rev. 1 20 Freescale Semiconductor
Clock Configuration Modes
Table 13. Clock Default Configurations
MODCK[1-3] 100 101 110 111 Input Clock Frequency 66 MHz 66 MHz 66 MHz 66 MHz CPM Multiplication Factor 2 2 2.5 2.5 CPM Frequency 133 MHz 133 MHz 166 MHz 166 MHz Core Multiplication Factor 2.5 3 2.5 3 Core Frequency 166 MHz 200 MHz 166 MHz 200 MHz
Table 14 describes all possible clock configurations when using the hard reset configuration sequence. Note also that basic modes are shown in boldface type. The frequencies listed are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user's device.
Table 14. Clock Configuration Modes 1
MODCK_H-MODCK[1-3] 0001_000 0001_001 0001_010 0001_011 0001_100 Core Multiplication Input Clock CPM Multiplication CPM Core Factor2 Factor2 Frequency2,3 Frequency2 Frequency2 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 2 2 2 2 2 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 4 5 6 7 8 133 MHz 166 MHz 200 MHz 233 MHz 266 MHz
0001_101 0001_110 0001_111 0010_000 0010_001
33 MHz 33 MHz 33 MHz 33 MHz 33 MHz
3 3 3 3 3
100 MHz 100 MHz 100 MHz 100 MHz 100 MHz
4 5 6 7 8
133 MHz 166 MHz 200 MHz 233 MHz 266 MHz
0010_010 0010_011 0010_100 0010_101 0010_110
33 MHz 33 MHz 33 MHz 33 MHz 33 MHz
4 4 4 4 4
133 MHz 133 MHz 133 MHz 133 MHz 133 MHz
4 5 6 7 8
133 MHz 166 MHz 200 MHz 233 MHz 266 MHz
0010_111 0011_000 0011_001 0011_010 0011_011
33 MHz 33 MHz 33 MHz 33 MHz 33 MHz
5 5 5 5 5
166 MHz 166 MHz 166 MHz 166 MHz 166 MHz
4 5 6 7 8
133 MHz 166 MHz 200 MHz 233 MHz 266 MHz
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 21
Clock Configuration Modes
Table 14. Clock Configuration Modes 1 (continued)
MODCK_H-MODCK[1-3] Core Multiplication Input Clock CPM Multiplication CPM Core Factor2 Factor2 Frequency2,3 Frequency2 Frequency2
0011_100 0011_101 0011_110 0011_111 0100_000
33 MHz 33 MHz 33 MHz 33 MHz 33 MHz
6 6 6 6 6
200 MHz 200 MHz 200 MHz 200 MHz 200 MHz
4 5 6 7 8
133 MHz 166 MHz 200 MHz 233 MHz 266 MHz
0100_001 0100_010 0100_011 0100_100 0100_101 0100_110
Reserved
0100_111 0101_000 0101_001 0101_010 0101_011 0101_100
Reserved
0101_101 0101_110 0101_111 0110_000 0110_001 0110_010
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
2 2 2 2 2 2
133 MHz 133 MHz 133 MHz 133 MHz 133 MHz 133 MHz
2 2.5 3 3.5 4 4.5
133 MHz 166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
0110_011 0110_100 0110_101 0110_110 0110_111 0111_000
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
2.5 2.5 2.5 2.5 2.5 2.5
166 MHz 166 MHz 166 MHz 166 MHz 166 MHz 166 MHz
2 2.5 3 3.5 4 4.5
133 MHz 166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
MPC8250 Hardware Specifications, Rev. 1 22 Freescale Semiconductor
Clock Configuration Modes
Table 14. Clock Configuration Modes 1 (continued)
MODCK_H-MODCK[1-3] Core Multiplication Input Clock CPM Multiplication CPM Core Factor2 Factor2 Frequency2,3 Frequency2 Frequency2
0111_001 0111_010 0111_011 0111_100 0111_101 0111_110
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
3 3 3 3 3 3
200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz
2 2.5 3 3.5 4 4.5
133 MHz 166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
0111_111 1000_000 1000_001 1000_010 1000_011 1000_100
1 2
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
3.5 3.5 3.5 3.5 3.5 3.5
233 MHz 233 MHz 233 MHz 233 MHz 233 MHz 233 MHz
2 2.5 3 3.5 4 4.5
133 MHz 166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
Because of speed dependencies, not all of the possible configurations in Table 14 are applicable. The user should choose the input clock frequency and the multiplication factors such that the frequency of the CPU is equal to or greater than 133 MHz (150 MHz for extended temperature parts) and the CPM ranges between 66-233 MHz. 3 Input clock frequency is given only for the purpose of reference. User should set MODCK_H-MODCK_L so that the resulting configuration does not exceed the frequency rating of the user's part.
3.2
PCI Mode
The PCI mode is selected according to three input pins, as shown in Table 12. In addition, note the following:
NOTE: PCI_MODCK
In PCI mode only, PCI_MODCK comes from the LGPL5 pin and MODCK_H[0-3] comes from {LGPL0, LGPL1, LGPL2, LGPL3}.
NOTE: Tval (Output Hold)
The minimum Tval = 2 when PCI_MODCK = 1, and the minimum Tval = 1 when PCI_MODCK = 0. Therefore, designers should use clock configurations that fit this condition to achieve PCI-compliant AC timing.
NOTE
Clock configurations change only after POR is asserted.
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 23
Clock Configuration Modes
3.2.1
PCI Host Mode
The frequencies listed are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user's device.
Table 15. Clock Default Configurations in PCI Host Mode (MODCK_HI = 0000)
Core CPM Input Clock Core PCI Division CPM PCI Multiplication MODCK[1-3]1 Frequency Multiplication Frequency Factor 2 Frequency Frequency2 Factor Factor (Bus) 000 001 010 011 100 101 110 111
1 2
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
2 2 2.5 2.5 2.5 3 3 3
133 MHz 133 MHz 166 MHz 166 MHz 166 MHz 200 MHz 200 MHz 200 MHz
2.5 3 3 3.5 4 3 3.5 4
166 MHz 200 MHz 200 MHz 233 MHz 266 MHz 200 MHz 233 MHz 266 MHz
2/4 2/4 3/6 3/6 3/6 3/6 3/6 3/6
66/33 MHz 66/33 MHz 55/28 MHz 55/28 MHz 55/28 MHz 66/33 MHz 66/33 MHz 66/33 MHz
Assumes MODCK_HI = 0000. The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic `1'), the PCI frequency is divided by 2 (33 instead of 66 MHz, etc.) Refer to Table 12.
Table 16 describes all possible clock configurations when using the MPC8250's internal PCI bridge in host mode.
Table 16. Clock Configuration Modes in PCI Host Mode
MODCK_H - MODCK[1- 3] 0001_000 0001_001 0001_010 0001_011 Input Clock Frequency 1 (Bus) 33 MHz 33 MHz 33 MHz 33 MHz CPM Core CPM Core PCI Division PCI Multiplication Multiplication Frequency Frequency Factor 2 Frequency2 Factor Factor 3 3 3 3 100 MHz 100 MHz 100 MHz 100 MHz 5 6 7 8 166 MHz 200 MHz 233 MHz 266 MHz 3/6 3/6 3/6 3/6 33/16 MHz 33/16 MHz 33/16 MHz 33/16 MHz
0010_000 0010_001 0010_010 0010_011
33 MHz 33 MHz 33 MHz 33 MHz
4 4 4 4
133 MHz 133 MHz 133 MHz 133 MHz
5 6 7 8
166 MHz 200 MHz 233 MHz 266 MHz
4/8 4/8 4/8 4/8
33/16 MHz 33/16 MHz 33/16 MHz 33/16 MHz
0011_000 3 0011_0013 0011_010
3
33 MHz 33 MHz 33 MHz
5 5 5
166 MHz 166 MHz 166 MHz
5 6 7
166 MHz 200 MHz 233 MHz
5 5 5
33 MHz 33 MHz 33 MHz
MPC8250 Hardware Specifications, Rev. 1 24 Freescale Semiconductor
Clock Configuration Modes
Table 16. Clock Configuration Modes in PCI Host Mode (continued)
MODCK_H - MODCK[1- 3] 0011_0113 Input Clock Frequency 1 (Bus) 33 MHz Core CPM Core PCI Division CPM PCI Multiplication Multiplication Frequency Factor 2 Frequency Frequency2 Factor Factor 5 166 MHz 8 266 MHz 5 33 MHz
0100_0003 0100_0013 0100_0103 0100_0113
33 MHz 33 MHz 33 MHz 33 MHz
6 6 6 6
200 MHz 200 MHz 200 MHz 200 MHz
5 6 7 8
166 MHz 200 MHz 233 MHz 266 MHz
6 6 6 6
33 MHz 33 MHz 33 MHz 33 MHz
0101_000 0101_001 0101_010 0101_011 0101_100
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
2 2 2 2 2
133 MHz 133 MHz 133 MHz 133 MHz 133 MHz
2.5 3 3.5 4 4.5
166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
2/4 2/4 2/4 2/4 2/4
66/33 MHz 66/33 MHz 66/33 MHz 66/33 MHz 66/33 MHz
0110_000 0110_001 0110_010 0110_011 0110_100
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
2.5 2.5 2.5 2.5 2.5
166 MHz 166 MHz 166 MHz 166 MHz 166 MHz
2.5 3 3.5 4 4.5
166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
3/6 3/6 3/6 3/6 3/6
55/28 MHz 55/28 MHz 55/28 MHz 55/28 MHz 55/28 MHz
0111_000 0111_001 0111_010 0111_011 0111_100
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
3 3 3 3 3
200 MHz 200 MHz 200 MHz 200 MHz 200 MHz
2.5 3 3.5 4 4.5
166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
3/6 3/6 3/6 3/6 3/6
66/33 MHz 66/33 MHz 66/33 MHz 66/33 MHz 66/33 MHz
1000_000 1000_001 1000_010 1000_011 1000_100
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
3 3 3 3 3
200 MHz 200 MHz 200 MHz 200 MHz 200 MHz
2.5 3 3.5 4 4.5
166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
4/8 4/8 4/8 4/8 4/8
50/25 MHz 50/25 MHz 50/25 MHz 50/25 MHz 50/25 MHz
1001_000 1001_001
66 MHz 66 MHz
3.5 3.5
233 MHz 233 MHz
2.5 3
166 MHz 200 MHz
4/8 4/8
58/29 MHz 58/29 MHz
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 25
Clock Configuration Modes
Table 16. Clock Configuration Modes in PCI Host Mode (continued)
MODCK_H - MODCK[1- 3] 1001_010 1001_011 1001_100 Input Clock Frequency 1 (Bus) 66 MHz 66 MHz 66 MHz Core CPM Core PCI Division CPM PCI Multiplication Multiplication Frequency Factor 2 Frequency Frequency2 Factor Factor 3.5 3.5 3.5 233 MHz 233 MHz 233 MHz 3.5 4 4.5 233 MHz 266 MHz 300 MHz 4/8 4/8 4/8 58/29 MHz 58/29 MHz 58/29 MHz
1010_000 1010_001 1010_010 1010_011 1010_100
100 MHz 100 MHz 100 MHz 100 MHz 100 MHz
2 2 2 2 2
200 MHz 200 MHz 200 MHz 200 MHz 200 MHz
2 2.5 3 3.5 4
200 MHz 250 MHz 300 MHz 350 MHz 400 MHz
3/6 3/6 3/6 3/6 3/6
66/33 MHz 66/33 MHz 66/33 MHz 66/33 MHz 66/33 MHz
1011_000 1011_001 1011_010 1011_011 1011_100
1
100 MHz 100 MHz 100 MHz 100 MHz 100 MHz
2.5 2.5 2.5 2.5 2.5
250 MHz 250 MHz 250 MHz 250 MHz 250 MHz
2 2.5 3 3.5 4
200 MHz 250 MHz 300 MHz 350 MHz 400 MHz
4/8 4/8 4/8 4/8 4/8
62/31 MHz 62/31MHz 62/31 MHz 62/31 MHz 62/31 MHz
Input clock frequency is given only for the purpose of reference. User should set MODCK_H-MODCK_L so that the resulting configuration does not exceed the frequency rating of the user's part. 2 The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic `1'), the PCI frequency is divided by 2 (33 instead of 66 MHz, etc.). Refer to Table 12 3 In this mode, PCI_MODCK must be "0".
3.2.2
PCI Agent Mode
The frequencies listed are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user's device.
Table 17. Clock Default Configurations in PCI Agent Mode (MODCK_HI = 0000)
Core Input Clock CPM Core CPM Bus Division 60x Bus Multiplication MODCK[1-3]1 Frequency Multiplication Frequency 3 Frequency Factor Frequency 4 2 2 Factor (PCI) Factor 000 001 010 011 66/33 MHz 66/33 MHz 66/33 MHz 66/33 MHz 2/4 2/4 3/6 3/6 133 MHz 133 MHz 200 MHz 200 MHz 2.5 3 3 4 166 MHz 200 MHz 200 MHz 266 MHz 2 2 3 3 66 MHz 66 MHz 66 MHz 66 MHz
MPC8250 Hardware Specifications, Rev. 1 26 Freescale Semiconductor
Clock Configuration Modes
Table 17. Clock Default Configurations in PCI Agent Mode (MODCK_HI = 0000)
Core Input Clock CPM Core CPM Bus Division 60x Bus Multiplication MODCK[1-3]1 Frequency Multiplication Frequency 3 Frequency Factor Frequency 4 Factor (PCI)2 Factor 2 100 101 110 111
1 2
66/33 MHz 66/33 MHz 66/33 MHz 66/33 MHz
3/6 3/6 4/8 4/8
200 MHz 200 MHz 266 MHz 266 MHz
3 3.5 3.5 3
240 MHz 280 MHz 300 MHz 300 MHz
2.5 2.5 3 2.5
80 MHz 80 MHz 88 MHz 100 MHz
Assumes MODCK_HI = 0000. The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic `1'), the PCI frequency is divided by 2 (33 instead of 66 MHz, etc.) and the CPM multiplication factor is multiplied by 2. Refer to Table 12 3 Core frequency = (60x bus frequency)(core multiplication factor) 4 Bus frequency = CPM frequency / bus division factor
Table 18 describes all possible clock configurations when using the MPC8250's internal PCI bridge in agent mode.
Table 18. Clock Configuration Modes in PCI Agent Mode
MODCK_H Input Clock Core CPM Core - CPM Bus Division 60x Bus Frequency Multiplication Multiplication Frequency 3 MODCK[1- Frequency Factor Frequency 4 (PCI) 1, 2 Factor Factor1 3] 0001_001 0001_010 0001_011 0001_100 66/33 MHz 66/33 MHz 66/33 MHz 66/33 MHz 2/4 2/4 2/4 2/4 133 MHz 133 MHz 133 MHz 133 MHz 5 6 7 8 166 MHz 200 MHz 233 MHz 266 MHz 4 4 4 4 33 MHz 33 MHz 33 MHz 33 MHz
0010_001 0010_010 0010_011 0010_100
50/25 MHz 50/25 MHz 50/25 MHz 50/25 MHz
3/6 3/6 3/6 3/6
150 MHz 150 MHz 150 MHz 150 MHz
3 3.5 4 4.5
180 MHz 210 MHz 240 MHz 270 MHz
2.5 2.5 2.5 2.5
60 MHz 60 MHz 60 MHz 60 MHz
0011_000 0011_001 0011_010 0011_011 0011_100
66/33 MHz 66/33 MHz 66/33 MHz 66/33 MHz 66/33 MHz
2/4 2/4 2/4 2/4 2/4
133 MHz 133 MHz 133 MHz 133 MHz 133 MHz
2.5 3 3.5 4 4.5
110MHz 132 MHz 154 MHz 176MHz 198 MHz
3 3 3 3 3
44 MHz 44 MHz 44 MHz 44 MHz 44 MHz
0100_000 0100_001 0100_010
66/33 MHz 66/33 MHz 66/33 MHz
3/6 3/6 3/6
200 MHz 200 MHz 200 MHz
2.5 3 3.5
166 MHz 200 MHz 233 MHz
3 3 3
66 MHz 66 MHz 66 MHz
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 27
Clock Configuration Modes
Table 18. Clock Configuration Modes in PCI Agent Mode (continued)
MODCK_H Input Clock Core CPM Core - CPM Bus Division 60x Bus Frequency Multiplication Multiplication Frequency 3 MODCK[1- Frequency Factor Frequency 4 1, 2 1 (PCI) Factor Factor 3] 0100_011 0100_100 66/33 MHz 66/33 MHz 3/6 3/6 200 MHz 200 MHz 4 4.5 266 MHz 300 MHz 3 3 66 MHz 66 MHz
0101_000 5 0101_0015 0101_0105 0101_0115 0101_1005
33 MHz 33 MHz 33 MHz 33 MHz 33 MHz
5 5 5 5 5
166 MHz 166 MHz 166 MHz 166 MHz 166 MHz
2.5 3 3.5 4 4.5
166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
2.5 2.5 2.5 2.5 2.5
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
0110_000 0110_001 0110_010 0110_011 0110_100
50/25 MHz 50/25 MHz 50/25 MHz 50/25 MHz 50/25 MHz
4/8 4/8 4/8 4/8 4/8
200 MHz 200 MHz 200 MHz 200 MHz 200 MHz
2.5 3 3.5 4 4.5
166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
3 3 3 3 3
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
0111_000 0111_001 0111_010 0111_011
66/33 MHz 66/33 MHz 66/33 MHz 66/33 MHz
3/6 3/6 3/6 3/6
200 MHz 200 MHz 200 MHz 200 MHz
2 2.5 3 3.5
200 MHz 250 MHz 300 MHz 350 MHz
2 2 2 2
100 MHz 100 MHz 100 MHz 100 MHz
1000_000 1000_001 1000_010 1000_011 1000_100 1000_101
66/33 MHz 66/33 MHz 66/33 MHz 66/33 MHz 66/33 MHz 66/33 MHz
3/6 3/6 3/6 3/6 3/6 3/6
200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz
2 2.5 3 3.5 4 4.5
160 MHz 200 MHz 240 MHz 280 MHz 320 MHz 360 MHz
2.5 2.5 2.5 2.5 2.5 2.5
80 MHz 80 MHz 80 MHz 80 MHz 80 MHz 80 MHz
1001_000 1001_001 1001_010 1001_011 1001_100
66/33 MHz 66/33 MHz 66/33 MHz 66/33 MHz 66/33 MHz
4/8 4/8 4/8 4/8 4/8
266 MHz 266 MHz 266 MHz 266 MHz 266 MHz
2.5 3 3.5 4 4.5
166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
4 4 4 4 4
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
MPC8250 Hardware Specifications, Rev. 1 28 Freescale Semiconductor
Pinout
Table 18. Clock Configuration Modes in PCI Agent Mode (continued)
MODCK_H Input Clock Core CPM Core - CPM Bus Division 60x Bus Frequency Multiplication Multiplication Frequency 3 MODCK[1- Frequency Factor Frequency 4 1, 2 1 (PCI) Factor Factor 3] 1010_000 1010_001 1010_010 1010_011 1010_100 66/33 MHz 66/33 MHz 66/33 MHz 66/33 MHz 66/33 MHz 4/8 4/8 4/8 4/8 4/8 266 MHz 266 MHz 266 MHz 266 MHz 266 MHz 2.5 3 3.5 4 4.5 222 MHz 266 MHz 300 MHz 350 MHz 400 MHz 3 3 3 3 3 88 MHz 88 MHz 88 MHz 88 MHz 88 MHz
1011_000 1011_001 1011_010 1011_011 1011_100
1 2 3 4 5
66/33 MHz 66/33 MHz 66/33 MHz 66/33 MHz 66/33 MHz
4/8 4/8 4/8 4/8 4/8
266 MHz 266 MHz 266 MHz 266 MHz 266 MHz
2 2.5 3 3.5 4
212MHz 265 MHz 318 MHz 371 MHz 424 MHz
2.5 2.5 2.5 2.5 2.5
106 MHz 106 MHz 106 MHz 106 MHz 106 MHz
The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic `1'), the PCI frequency is divided by 2 (33 instead of 66 MHz, etc.) and the CPM multiplication factor is multiplied by 2. Refer to Table 12 Input clock frequency is given only for the purpose of reference. User should set MODCK_H-MODCK_L so that the resulting configuration does not exceed the frequency rating of the user's part. Core frequency = (60x bus frequency)(core multiplication factor) Bus frequency = CPM frequency / bus division factor In this mode, PCI_MODCK must be "1".
4
4.1
Pinout
ZU Package
This section provides the pin assignments and pinout list for the MPC8250.
The following figures and table represent the standard 480 TBGA package. For information on the alternate package, refer to Section 4.2, "VR Package" on page 42.
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 29
Pinout
4.1.1
ZU Pin Assignments
Figure 13 shows the pinout of the ZU package as viewed from the top surface.
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ 1 2 3 456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Not to Scale
2
3
456
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ
Figure 13. Pinout of the 480 TBGA Package as Viewed from the Top Surface
MPC8250 Hardware Specifications, Rev. 1 30 Freescale Semiconductor
Pinout
Figure 14 shows the side profile of the TBGA package to indicate the direction of the top surface view.
View
Copper Heat Spreader (Oxidized for Insulation) Polymide Tape Die Soldermask Glob-Top Filled Area Glob-Top Dam 1.27 mm Pitch Wire Bonds Copper Traces Die Attach Etched Cavity Pressure Sensitive Adhesive
Figure 14. Side View of the TBGA Package
Table 19 shows the pinout list of the ZU package of the MPC8250. Table 20 defines conventions and acronyms used in Table 19.
Table 19. MPC8250 ZU Package Pinout List
Pin Name BR BG ABB/IRQ2 TS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 Ball W5 F4 E2 E3 G1 H5 H2 H1 J5 J4 J3 J2 J1 K4 K3 K2 K1 L5 L4 L3 L2 L1
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 31
Pinout
Table 19. MPC8250 ZU Package Pinout List (continued)
Pin Name A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 TT0 TT1 TT2 TT3 TT4 TBST TSIZ0 TSIZ1 TSIZ2 TSIZ3 AACK ARTRY DBG DBB/IRQ3 D0 D1 D2 D3 D4 D5 D6 Ball M5 N5 N4 N3 N2 N1 P4 P3 P2 P1 R1 R3 R5 R4 F1 G4 G3 G2 F2 D3 C1 E4 D2 F5 F3 E1 V1 V2 B20 A18 A16 A13 E12 D9 A6
MPC8250 Hardware Specifications, Rev. 1 32 Freescale Semiconductor
Pinout
Table 19. MPC8250 ZU Package Pinout List (continued)
Pin Name D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 Ball B5 A20 E17 B15 B13 A11 E9 B7 B4 D19 D17 D15 C13 B11 A8 A5 C5 C19 C17 C15 D13 C11 B8 A4 E6 E18 B17 A15 A12 D11 C8 E7 A3 D18 A17
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 33
Pinout
Table 19. MPC8250 ZU Package Pinout List (continued)
Pin Name D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 DP0/RSRV/EXT_BR2 IRQ1/DP1/EXT_BG2 IRQ2/DP2/TLBISYNC/EXT_DBG2 IRQ3/DP3/CKSTP_OUT/EXT_BR3 IRQ4/DP4/CORE_SRESET/EXT_BG3 IRQ5/DP5/TBEN/EXT_DBG3 IRQ6/DP6/CSE0 IRQ7/DP7/CSE1 PSDVAL TA TEA GBL/IRQ1 CI/BADDR29/IRQ2 Ball A14 B12 A10 D8 B6 C4 C18 E16 B14 C12 B10 A7 C6 D5 B18 B16 E14 D12 C10 E8 D6 C2 B22 A22 E21 D21 C21 B21 A21 E20 V3 C22 V5 W1 U2
MPC8250 Hardware Specifications, Rev. 1 34 Freescale Semiconductor
Pinout
Table 19. MPC8250 ZU Package Pinout List (continued)
Pin Name WT/BADDR30/IRQ3 L2_HIT/IRQ4 CPU_BG/BADDR31/IRQ5 CPU_DBG CPU_BR CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 CS10/BCTL1 CS11/AP0 BADDR27 BADDR28 ALE BCTL0 PWE0/PSDDQM0/PBS0 PWE1/PSDDQM1/PBS1 PWE2/PSDDQM2/PBS2 PWE3/PSDDQM3/PBS3 PWE4/PSDDQM4/PBS4 PWE5/PSDDQM5/PBS5 PWE6/PSDDQM6/PBS6 PWE7/PSDDQM7/PBS7 PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 Ball U3 Y4 U4 R2 Y3 F25 C29 E27 E28 F26 F27 F28 G25 D29 E29 F29 G28 T5 U1 T2 A27 C25 E24 D24 C24 B26 A26 B25 A25 E23 B24 A24 B23 A23 D22
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 35
Pinout
Table 19. MPC8250 ZU Package Pinout List (continued)
Pin Name LWE0/LSDDQM0/LBS0/PCI_CFG0 LWE1/LSDDQM1/LBS1/PCI_CFG1 LWE2/LSDDQM2/LBS2/PCI_CFG2 LWE3/LSDDQM3/LBS3/PCI_CFG3 LSDA10/LGPL0/PCI_MODCKH0 LSDWE/LGPL1/PCI_MODCKH1 LOE/LSDRAS/LGPL2/PCI_MODCKH2 LSDCAS/LGPL3/PCI_MODCKH3 LGTA/LUPMWAIT/LGPL4/LPBS LGPL5/LSDAMUX/PCI_MODCK LWR L_A14/PAR L_A15/FRAME/SMI L_A16/TRDY L_A17/IRDY/CKSTP_OUT L_A18/STOP L_A19/DEVSEL L_A20/IDSEL L_A21/PERR L_A22/SERR L_A23/REQ0 L_A24/REQ1/HSEJSW L_A25/GNT0 L_A26/GNT1/HSLED L_A27/GNT2/HSENUM L_A28/RST/CORE_SRESET L_A29/INTA L_A30/REQ2 L_A31/DLLOUT LCL_D0/AD0 LCL_D1/AD1 LCL_D2/AD2 LCL_D3/AD3 LCL_D4/AD4 LCL_D5/AD5 Ball H28 H27 H26 G29 D27 C28 E26 D25 C26 B27 D28 N27 T29 R27 R26 R29 R28 W29 P28 N26 AA27 P29 AA26 N25 AA25 AB29 AB28 P25 AB27 H29 J29 J28 J27 J26 J25
MPC8250 Hardware Specifications, Rev. 1 36 Freescale Semiconductor
Pinout
Table 19. MPC8250 ZU Package Pinout List (continued)
Pin Name LCL_D6/AD6 LCL_D7/AD7 LCL_D8/AD8 LCL_D9/AD9 LCL_D10/AD10 LCL_D11/AD11 LCL_D12/AD12 LCL_D13/AD13 LCL_D14/AD14 LCL_D15/AD15 LCL_D16/AD16 LCL_D17/AD17 LCL_D18/AD18 LCL_D19/AD19 LCL_D20/AD20 LCL_D21/AD21 LCL_D22/AD22 LCL_D23/AD23 LCL_D24/AD24 LCL_D25/AD25 LCL_D26/AD26 LCL_D27/AD27 LCL_D28/AD28 LCL_D29/AD29 LCL_D30/AD30 LCL_D31/AD31 LCL_DP0/C0/BE0 LCL_DP1/C1/BE1 LCL_DP2/C2/BE2 LCL_DP3/C3/BE3 IRQ0/NMI_OUT IRQ7/INT_OUT/APE TRST TCK TMS Ball K25 L29 L27 L26 L25 M29 M28 M27 M26 N29 T25 U27 U26 U25 V29 V28 V27 V26 W27 W26 W25 Y29 Y28 Y25 AA29 AA28 L28 N28 T28 W28 T1 D1 AH3 AG5 AJ3
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 37
Pinout
Table 19. MPC8250 ZU Package Pinout List (continued)
Pin Name TDI TDO TRIS PORESET HRESET SRESET QREQ RSTCONF MODCK1/AP1/TC0/BNKSEL0 MODCK2/AP2/TC1/BNKSEL1 MODCK3/AP3/TC2/BNKSEL2 XFC CLKIN1 PA0/RESTART1/DREQ3 PA1/REJECT1/DONE3 PA2/CLK20/DACK3 PA3/CLK19/DACK4/L1RXD1A2 PA4/REJECT2/DONE4 PA5/RESTART2/DREQ4 PA6 PA7/SMSYN2 PA8/SMRXD2 PA9/SMTXD2 PA10/MSNUM5 PA11/MSNUM4 PA12/MSNUM3 PA13/MSNUM2 PA14/FCC1_RXD3 PA15/FCC1_RXD2 PA16/FCC1_RXD1 PA17/FCC1_RXD0/FCC1_RXD PA18/FCC1_TXD0/FCC1_TXD PA19/FCC1_TXD1 PA20/FCC1_TXD2 PA21/FCC1_TXD3 Ball AE6 AF5 AB4 AG6 AH5 AF6 AA3 AJ4 W2 W3 W4 AB2 AH4 AC29 1 AC251 AE281 AG291 AG281 AG261 AE241 AH251 AF231 AH231 AE221 AH221 AJ211 AH201 AG191 AF181 AF171 AE161 AJ161 AG151 AJ131 AE131
MPC8250 Hardware Specifications, Rev. 1 38 Freescale Semiconductor
Pinout
Table 19. MPC8250 ZU Package Pinout List (continued)
Pin Name PA22 PA23 PA24/MSNUM1 PA25/MSNUM0 PA26/FCC1_MII_RX_ER PA27/FCC1_MII_RX_DV PA28/FCC1_MII_TX_EN PA29/FCC1_MII_TX_ER PA30/FCC1_MII_CRS/FCC1_RTS PA31/FCC1_MII_COL PB4/FCC3_TXD3/L1RSYNCA2/FCC3_RTS PB5/FCC3_TXD2/L1TSYNCA2/L1GNTA2 PB6/FCC3_TXD1/L1RXDA2/L1RXD0A2 PB7/FCC3_TXD0/FCC3_TXD/L1TXDA2/L1TXD0A2 PB8/FCC3_RXD0/FCC3_RXD/TXD3 PB9/FCC3_RXD1/L1TXD2A2 PB10/FCC3_RXD2 PB11/FCC3_RXD3 PB12/FCC3_MII_CRS/TXD2 PB13/FCC3_MII_COL/L1TXD1A2 PB14/FCC3_MII_TX_EN/RXD3 PB15/FCC3_MII_TX_ER/RXD2 PB16/FCC3_MII_RX_ER/CLK18 PB17/FCC3_MII_RX_DV/CLK17 PB18/FCC2_RXD3/L1CLKOD2/L1RXD2A2 PB19/FCC2_RXD2/L1RQD2/L1RXD3A2 PB20/FCC2_RXD1/L1RSYNCD2/L1TXD1A1 PB21/FCC2_RXD0/FCC2_RXD/L1TSYNCD2/L1GNTD2 PB22/FCC2_TXD0/FCC2_TXD/L1RXDD2 PB23/FCC2_TXD1/L1TXDD2 PB24/FCC2_TXD2/L1RSYNCC2 PB25/FCC2_TXD3/L1TSYNCC2/L1GNTC2 PB26/FCC2_MII_CRS/L1RXDC2 PB27/FCC2_MII_COL/L1TXDC2 PB28/FCC2_MII_RX_ER/FCC2_RTS/L1TSYNCB2/L1GNTB2/TXD1 Ball AF121 AG111 AH91 AJ81 AH71 AF71 AD51 AF11 AD31 AB51 AD281 AD261 AD251 AE261 AH271 AG241 AH241 AJ241 AG221 AH211 AG201 AF191 AJ181 AJ171 AE141 AF131 AG121 AH111 AH161 AE151 AJ91 AE91 AJ71 AH61 AE31
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 39
Pinout
Table 19. MPC8250 ZU Package Pinout List (continued)
Pin Name PB29/L1RSYNCB2/FCC2_MII_TX_EN PB30/FCC2_MII_RX_DV/L1RXDB2 PB31/FCC2_MII_TX_ER/L1TXDB2 PC0/DREQ1/BRGO7/SMSYN2/L1CLKOA2 PC1/DREQ2/BRGO6/L1RQA2 PC2/FCC3_CD/DONE2 PC3/FCC3_CTS/DACK2/CTS4 PC4/SI2_L1ST4/FCC2_CD PC5/SI2_L1ST3/FCC2_CTS PC6/FCC1_CD PC7/FCC1_CTS PC8/CD4/RENA4/SI2_L1ST2/CTS3 PC9/CTS4/CLSN4/SI2_L1ST1/L1TSYNCA2/L1GNTA2 PC10/CD3/RENA3 PC11/CTS3/CLSN3/L1TXD3A2 PC12/CD2/RENA2 PC13/CTS2/CLSN2 PC14/CD1/RENA1 PC15/CTS1/CLSN1/SMTXD2 PC16/CLK16/TIN4 PC17/CLK15/TIN3/BRGO8 PC18/CLK14/TGATE2 PC19/CLK13/BRGO7/SPICLK PC20/CLK12/TGATE1 PC21/CLK11/BRGO6 PC22/CLK10/DONE1 PC23/CLK9/BRGO5/DACK1 PC24/CLK8/TOUT4 PC25/CLK7/BRGO4 PC26/CLK6/TOUT3/TMCLK PC27/FCC3_TXD/FCC3_TXD0/CLK5/BRGO3 PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2 PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1 PC30/CLK2/TOUT1 PC31/CLK1/BRGO1 Ball AE21 AC51 AC41 AB261 AD291 AE291 AE271 AF271 AF241 AJ261 AJ251 AF221 AE211 AF201 AE191 AE181 AH181 AH171 AG161 AF151 AJ151 AH141 AG131 AH121 AJ111 AG101 AE101 AF91 AE81 AJ61 AG21 AF31 AF21 AE11 AD11
MPC8250 Hardware Specifications, Rev. 1 40 Freescale Semiconductor
Pinout
Table 19. MPC8250 ZU Package Pinout List (continued)
Pin Name PD4/BRGO8/FCC3_RTS/SMRXD2 PD5/DONE1 PD6/DACK1 PD7/SMSYN1FCC1_TXCLAV2 PD8/SMRXD1/BRGO5 PD9/SMTXD1/BRGO3 PD10/L1CLKOB2/BRGO4 PD11/L1RQB2 PD12 PD13 PD14/L1CLKOC2/I2CSCL PD15/L1RQC2/I2CSDA PD16/SPIMISO PD17/BRGO2/SPIMOSI PD18/SPICLK PD19/SPISEL/BRGO PD20/RTS4/TENA4/L1RSYNCA2 PD21/TXD4/L1RXD0A2/L1RXDA2 PD22/RXD4/L1TXD0A2/L1TXDA2 PD23/RTS3/TENA3 PD24/TXD3 PD25/RXD3 PD26/RTS2/TENA2 PD27/TXD2 PD28/RXD2 PD29/RTS1/TENA1 PD30/TXD1 PD31/RXD1 VCCSYN VCCSYN1 GNDSYN CLKIN2 SPARE4 2 PCI_MODE 3 SPARE62 Ball AC281 AD271 AF291 AF281 AG251 AH261 AJ271 AJ231 AG231 AJ221 AE201 AJ201 AG181 AG171 AF161 AH151 AJ141 AH131 AJ121 AE121 AF101 AG91 AH81 AG71 AE41 AG11 AD41 AD21 AB3 B9 AB1 AE11 U5 AF25 V4
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 41
Pinout
Table 19. MPC8250 ZU Package Pinout List (continued)
Pin Name THERMAL0 4 THERMAL1 4 I/O power Ball AA1 AG4 AG21, AG14, AG8, AJ1, AJ2, AH1, AH2, AG3, AF4, AE5, AC27, Y27, T27, P27, K26, G27, AE25, AF26, AG27, AH28, AH29, AJ28, AJ29, C7, C14, C16, C20, C23, E10, A28, A29, B28, B29, C27, D26, E25, H3, M4, T3, AA4, A1, A2, B1, B2, C3, D4, E5 U28, U29, K28, K29, A9, A19, B19, M1, M2, Y1, Y2, AC1, AC2, AH19, AJ19, AH10, AJ10, AJ5 AA5, AF21, AF14, AF8, AE7, AF11, AE17, AE23, AC26, AB25, Y26, V25, T26, R25, P26, M25, K27, H25, G26, D7, D10, D14, D16, D20, D23, C9, E11, E13, E15, E19, E22, B3, G5, H4, K5, M3, P5, T4, Y5, AA2, AC3
Core Power
Ground
1
The default configuration of the CPM pins (PA[0-31], PB[4-31], PC[0-31], PD[4-31]) is input. To prevent excessive DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs. 2 Must be pulled down or left floating. 3 If PCI is not desired, this pin should be pulled up or left floating. 4 For information on how to use this pin, refer to MPC8260 PowerQUICC II Thermal Resistor Guide (AN2271/D) available at www.freescale.com.
Symbols used in Table 19 are described in Table 20.
Table 20. Symbol Legend
Symbol OVERBAR MII Meaning Signals with overbars, such as TA, are active low. Indicates that a signal is part of the media independent interface.
4.2
VR Package
The following figures and table represent the alternate 516 PBGA package. For information on the standard package for the MPC8250, refer to Section 4.1, "ZU Package" on page 29.
MPC8250 Hardware Specifications, Rev. 1 42 Freescale Semiconductor
Pinout
4.2.1
VR Pin Assignments
Figure 15 shows the pinout of the VR package as viewed from the top surface.
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1
Not to Scale
2
3
456
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
2
3
456
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Figure 15. Pinout of the 516 PBGA Package (View from Top)
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 43
Pinout
Figure 16 shows the side profile of the PBGA package to indicate the direction of the top surface view.
Transfer molding compound
Plated substrate via
Die attach
Wire bonds
Ball bond Screen-printed solder mask Cu substrate traces
DIE
1 mm pitch
BT resin glass epoxy
Figure 16. Side View of the PBGA Package
Table 21 shows the pinout list of the MPC8250VR. Table 20 defines conventions and acronyms used in Table 21.
Table 21. MPC8250 VR Package Pinout List
Pin Name BR BG ABB/IRQ2 TS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 Ball C16 D2 C1 D1 D5 E8 C4 B4 A4 D7 D8 C6 B5 B6 C7 C8 A6 D9 F11 B7 B8 C9 A7
MPC8250 Hardware Specifications, Rev. 1 44 Freescale Semiconductor
Pinout
Table 21. MPC8250 VR Package Pinout List (continued)
Pin Name A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 TT0 TT1 TT2 TT3 TT4 TBST TSIZ0 TSIZ1 TSIZ2 TSIZ3 AACK ARTRY DBG DBB/IRQ3 D0 D1 D2 D3 D4 D5 D6 D7 Ball B9 E11 A8 D11 B10 C11 A9 B11 C12 D12 A10 B12 B13 E7 B3 F8 A3 C3 F5 E3 E2 E1 E4 D3 C2 A14 C15 W4 Y1 V1 P4 N3 K5 J4 G1
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 45
Pinout
Table 21. MPC8250 VR Package Pinout List (continued)
Pin Name D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 Ball AB1 U4 U2 N6 N1 L1 J5 G3 AA2 W1 T3 T1 M2 K2 J1 G4 U5 T5 P5 P3 M3 K3 H2 G5 AA1 V2 U1 P2 M4 K4 H3 F2 Y2 U3 T2
MPC8250 Hardware Specifications, Rev. 1 46 Freescale Semiconductor
Pinout
Table 21. MPC8250 VR Package Pinout List (continued)
Pin Name D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 DP0/RSRV/EXT_BR2 IRQ1/DP1/EXT_BG2 IRQ2/DP2/TLBISYNC/EXT_DBG2 IRQ3/DP3/CKSTP_OUT/EXT_BR3 IRQ4/DP4/CORE_SRESET/EXT_BG3 IRQ5/DP5/TBEN/EXT_DBG3 IRQ6/DP6/CSE0 IRQ7/DP7/CSE1 PSDVAL TA TEA GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 Ball N2 M5 K1 H4 F1 W2 T4 R3 N4 M1 J2 H5 F3 V3 R5 R2 N5 L2 J3 H1 F4 AB3 W5 AC2 AA3 AD1 AC1 AB2 Y3 D15 Y4 D16 E15 D14 E14
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 47
Pinout
Table 21. MPC8250 VR Package Pinout List (continued)
Pin Name L2_HIT/IRQ4 CPU_BG/BADDR31/IRQ5 CPU_DBG CPU_BR CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 CS10/BCTL1 CS11/AP0 BADDR27 BADDR28 ALE BCTL0 PWE0/PSDDQM0/PBS0 PWE1/PSDDQM1/PBS1 PWE2/PSDDQM2/PBS2 PWE3/PSDDQM3/PBS3 PWE4/PSDDQM4/PBS4 PWE5/PSDDQM5/PBS5 PWE6/PSDDQM6/PBS6 PWE7/PSDDQM7/PBS7 PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 LWE0/LSDDQM0/LBS0/PCI_CFG0 Ball A17 B14 F13 B17 AC6 AD6 AE6 AB7 AF7 AC7 AD7 AF8 AE8 AD8 AC8 AB8 C13 A12 D13 AF4 AA5 AE4 AD4 AF3 AB4 AE3 AF2 AD3 AE2 AD2 AE1 AC3 W6 AA4 AC9
MPC8250 Hardware Specifications, Rev. 1 48 Freescale Semiconductor
Pinout
Table 21. MPC8250 VR Package Pinout List (continued)
Pin Name LWE1/LSDDQM1/LBS1/PCI_CFG1 LWE2/LSDDQM2/LBS2/PCI_CFG2 LWE3/LSDDQM3/LBS3/PCI_CFG3 LSDA10/LGPL0/PCI_MODCKH0 LSDWE/LGPL1/PCI_MODCKH1 LOE/LSDRAS/LGPL2/PCI_MODCKH2 LSDCAS/LGPL3/PCI_MODCKH3 LGTA/LUPMWAIT/LGPL4/LPBS LGPL5/LSDAMUX/PCI_MODCK LWR L_A14/PAR L_A15/FRAME/SMI L_A16/TRDY L_A17/IRDY/CKSTP_OUT L_A18/STOP L_A19/DEVSEL L_A20/IDSEL L_A21/PERR L_A22/SERR L_A23/REQ0 L_A24/REQ1/HSEJSW L_A25/GNT0 L_A26/GNT1/HSLED L_A27/GNT2/HSENUM L_A28/RST/CORE_SRESET L_A29/INTA L_A30/REQ2 L_A31/DLLOUT LCL_D0/AD0 LCL_D1/AD1 LCL_D2/AD2 LCL_D3/AD3 LCL_D4/AD4 LCL_D5/AD5 LCL_D6/AD6 Ball AD9 AE9 AF9 AB6 AF5 AE5 AD5 AC5 AB5 AF6 AE13 AD15 AF16 AF15 AE15 AE14 AC17 AD14 AF13 AE20 AC14 AC19 AD13 AF21 AF22 AE21 AB14 AD20 AB9 AB10 AC10 AD10 AE10 AF10 AF11
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 49
Pinout
Table 21. MPC8250 VR Package Pinout List (continued)
Pin Name LCL_D7/AD7 LCL_D8/AD8 LCL_D9/AD9 LCL_D10/AD10 LCL_D11/AD11 LCL_D12/AD12 LCL_D13/AD13 LCL_D14/AD14 LCL_D15/AD15 LCL_D16/AD16 LCL_D17/AD17 LCL_D18/AD18 LCL_D19/AD19 LCL_D20/AD20 LCL_D21/AD21 LCL_D22/AD22 LCL_D23/AD23 LCL_D24/AD24 LCL_D25/AD25 LCL_D26/AD26 LCL_D27/AD27 LCL_D28/AD28 LCL_D29/AD29 LCL_D30/AD30 LCL_D31/AD31 LCL_DP0/C0/BE0 LCL_DP1/C1/BE1 LCL_DP2/C2/BE2 LCL_DP3/C3/BE3 IRQ0/NMI_OUT IRQ7/INT_OUT/APE TRST TCK TMS TDI Ball AB12 AB11 AF12 AE11 AC13 AC12 AB13 AD12 AF14 AF17 AE16 AD16 AC16 AB16 AF18 AE17 AD17 AB17 AE18 AD18 AC18 AE19 AF20 AD19 AB18 AE12 AA13 AC15 AF19 A11 E5 F22 A24 C24 A25
MPC8250 Hardware Specifications, Rev. 1 50 Freescale Semiconductor
Pinout
Table 21. MPC8250 VR Package Pinout List (continued)
Pin Name TDO TRIS PORESET HRESET SRESET QREQ RSTCONF MODCK1/AP1/TC0/BNKSEL0 MODCK2/AP2/TC1/BNKSEL1 MODCK3/AP3/TC2/BNKSEL2 XFC CLKIN1 PA0/RESTART1/DREQ3 PA1/REJECT1/DONE3 PA2/CLK20/DACK3 PA3/CLK19/DACK4/L1RXD1A2 PA4/REJECT2/DONE4 PA5/RESTART2/DREQ4 PA6 PA7/SMSYN2 PA8/SMRXD2 PA9/SMTXD2 PA10/MSNUM5 PA11/MSNUM4 PA12/MSNUM3 PA13/MSNUM2 PA14/FCC1_RXD3 PA15/FCC1_RXD2 PA16/FCC1_RXD1 PA17/FCC1_RXD0/FCC1_RXD PA18/FCC1_TXD0/FCC1_TXD PA19/FCC1_TXD1 PA20/FCC1_TXD2 PA21/FCC1_TXD3 PA22 Ball B24 C19 B25 D24 E23 D18 E24 B16 F16 A15 A18 G22 AC20 1 AC211 AF251 AE241 AA211 AD251 AC241 AA221 AA231 Y261 W221 W231 V261 V251 T221 T251 R241 P221 N261 N231 K261 L231 K231
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 51
Pinout
Table 21. MPC8250 VR Package Pinout List (continued)
Pin Name PA23 PA24/MSNUM1 PA25/MSNUM0 PA26/FCC1_MII_RX_ER PA27/FCC1_MII_RX_DV PA28/FCC1_MII_TX_EN PA29/FCC1_MII_TX_ER PA30/FCC1_MII_CRS/FCC1_RTS PA31/FCC1_MII_COL PB4/FCC3_TXD3/L1RSYNCA2/ FCC3_RTS PB5/FCC3_TXD2/L1TSYNCA2/ L1GNTA2 PB6/FCC3_TXD1/L1RXDA2/L1RXD0A2 PB7/FCC3_TXD0/FCC3_TXD/ L1TXDA2/L1TXD0A2 PB8/FCC3_RXD0/FCC3_RXD/TXD3 PB9/FCC3_RXD1/L1TXD2A2 PB10/FCC3_RXD2 PB11/FCC3_RXD3 PB12/FCC3_MII_CRS/TXD2 PB13/FCC3_MII_COL/L1TXD1A2 PB14/FCC3_MII_TX_EN/RXD3 PB15/FCC3_MII_TX_ER/RXD2 PB16/FCC3_MII_RX_ER/CLK18 PB17/FCC3_MII_RX_DV/CLK17 PB18/FCC2_RXD3/L1CLKOD2/ L1RXD2A2 PB19FCC2_RXD2/L1RQD2/L1RXD3A2 PB20/FCC2_RXD1/L1RSYNCD2/ L1TXD1A1 PB21/FCC2_RXD0/FCC2_RXD/ L1TSYNCD2/L1GNTD2 PB22/FCC2_TXD0/FCC2_TXD/ L1RXDD2 PB23/FCC2_TXD1/L1TXDD2 PB24/FCC2_TXD2/L1RSYNCC2 PB25/FCC2_TXD3/L1TSYNCC2/ L1GNTC2 PB26/FCC2_MII_CRS/L1RXDC2 PB27/FCC2_MII_COL/L1TXDC2 PB28/FCC2_MII_RX_ER/FCC2_RTS/ L1TSYNCB2/L1GNTB2/TXD1 PB29/L1RSYNCB2/ FCC2_MII_TX_EN Ball H261 F251 D261 D251 C251 C221 B211 A201 A191 AD211 AD221 AC221 AE261 AB231 AC261 AB261 AA251 W261 W251 V241 U241 R221 R231 M231 L241 K241 L211 P251 N251 E261 H231 C261 B261 A221 A211
MPC8250 Hardware Specifications, Rev. 1 52 Freescale Semiconductor
Pinout
Table 21. MPC8250 VR Package Pinout List (continued)
Pin Name PB30/FCC2_MII_RX_DV/L1RXDB2 PB31/FCC2_MII_TX_ER/L1TXDB2 PC0/DREQ1/BRGO7/SMSYN2/ L1CLKOA2 PC1/DREQ2/BRGO6/L1RQA2 PC2/FCC3_CD/DONE2 PC3/FCC3_CTS/DACK2/CTS4 PC4/SI2_L1ST4/FCC2_CD PC5/SI2_L1ST3/FCC2_CTS PC6/FCC1_CD PC7/FCC1_CTS PC8/CD4/RENA4/SI2_L1ST2/CTS3 PC9/CTS4/CLSN4/SI2_L1ST1/ L1TSYNCA2/L1GNTA2 PC10/CD3/RENA3 PC11/CTS3/CLSN3/L1TXD3A2 PC12/CD2/RENA2 PC13/CTS2/CLSN2 PC14/CD1/RENA1 PC15/CTS1/CLSN1/SMTXD2 PC16/CLK16/TIN4 PC17/CLK15/TIN3/BRGO8 PC18/CLK14/TGATE2 PC19/CLK13/BRGO7/SPICLK PC20/CLK12/TGATE1 PC21/CLK11/BRGO6 PC22/CLK10/DONE1 PC23/CLK9/BRGO5/DACK1 PC24/CLK8/TOUT4 PC25/CLK7/BRGO4 PC26/CLK6/TOUT3/TMCLK PC27/FCC3_TXD/FCC3_TXD0/CLK5/ BRGO3 PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2 PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1 PC30/CLK2/TOUT1 PC31/CLK1/BRGO1 PD4/BRGO8/FCC3_RTS/SMRXD2 Ball E201 C201 AE221 AA191 AF241 AE251 AB221 AC251 AB251 AA241 Y241 U221 V231 U231 T261 R261 P261 P241 M261 L261 M241 L221 K251 J251 G261 F261 G241 E251 G231 B231 E221 E211 D211 B201 AF231
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 53
Pinout
Table 21. MPC8250 VR Package Pinout List (continued)
Pin Name PD5/DONE1 PD6/DACK1 PD7/SMSYN1/FCC1_TXCLAV2 PD8/SMRXD1/BRGO5 PD9/SMTXD1/BRGO3 PD10/L1CLKOB2/BRGO4 PD11/L1RQB2 PD12 PD13 PD14/L1CLKOC2/I2CSCL PD15/L1RQC2/I2CSDA PD16/SPIMISO PD17/BRGO2/SPIMOSI PD18/SPICLK PD19/SPISEL/BRGO1 PD20/RTS4/TENA4/L1RSYNCA2 PD21/TXD4/L1RXD0A2/L1RXDA2 PD22/RXD4L1TXD0A2/L1TXDA2 PD23/RTS3/TENA3 PD24/TXD3 PD25/RXD3 PD26/RTS2/TENA2 PD27/TXD2 PD28/RXD2 PD29/RTS1/TENA1 PD30/TXD1 PD31/RXD1 VCCSYN VCCSYN1 GNDSYN CLKIN2 SPARE4 2 PCI_MODE 3 SPARE62 THERMAL0 4 Ball AE231 AB211 AD231 AD261 Y221 AB241 Y231 AA261 W241 V221 U261 T231 R251 P231 N221 M251 L251 J261 K221 G251 H241 F241 H221 B221 D221 C211 E191 D19 K6 B18 K21 C14 AD24 B15 E17
MPC8250 Hardware Specifications, Rev. 1 54 Freescale Semiconductor
Package Description
Table 21. MPC8250 VR Package Pinout List (continued)
Pin Name THERMAL14 I/O power Ball C23 E6, F6, H6, L5, L6, P6, T6, U6, V5, Y5, AA6, AA8, AA10, AA11, AA14, AA16, AA17, AB19, AB20, W21, U21, T21, P21, N21, M22, J22, H21, F21, F19, F17, E16, F14, E13, E12, F10, E10, E9 L3, V4, W3, AC11, AD11, AB15, U25, T24, J24, H25, F23, B19, D17, C17, D10, C10 A2, B1, B2, A5, C5, C18, D4, D6, G2, L4, P1, R1, R4, AC4, AE7, AC23, Y25, N24, J23, A23, D23, D20, E18, A13, A16, K10, K11, K12, K13, K14, K15, K16, K17, L10, L11, L12, L13, L14, L15, L16, L17, M10, M11, M12, M13, M14, M15, M16, M17, N10, N11, N12, N13, N14, N15, N16, N17, P10, P11, P12, P13, P14, P15, P16, P17, R10, R11,R12, R13, R14, R15, R16, R17, T10, T11, T12, T13, T14, T15, T16, T17, U10, U11, U12, U13, U14, U15, U16, U17
Core Power
Ground
1
The default configuration of the CPM pins (PA[0-31], PB[4-31], PC[0-31], PD[4-31]) is input. To prevent excessive DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs. 2 Must be pulled down or left floating. 3 If PCI is not desired, must be pulled up or left floating. 4 For information on how to use this pin, refer to MPC8260 PowerQUICC II Thermal Resistor Guide (AN2271/D).
5
5.1
Package Description
Package Parameters
Table 22. Package Parameters
Package ZU VR Devices MPC8250 MPC8250VR Outline (mm) 37.5 x 37.5 27 x 27 Type TBGA PBGA Interconnects 480 516 Pitch (mm) 1.27 1 Nominal Unmounted Height (mm) 1.55 2.25
The following sections provide the package parameters and mechanical dimensions.
Package parameters are provided in Table 22.
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 55
Package Description
5.2
5.2.1
Mechanical Dimensions
ZU Package Dimensions
Figure 17 provides the mechanical dimensions and bottom surface nomenclature of the 480 TBGA package.
Notes: 1. Dimensions and Tolerancing per ASME Y14.5M-1994. 2. Dimensions in millimeters. 3. Dimension b is measured at the
Millimeters Dim Min A A1 A2 A3 b D D1 e E E1 1.45 0.60 0.85 0.25 0.65 Max 1.65 0.70 0.95 -- 0.85
37.50 BSC 35.56 REF 1.27 BSC 37.50 BSC 35 56 REF
Figure 17. Mechanical Dimensions and Bottom Surface Nomenclature--480 TBGA
MPC8250 Hardware Specifications, Rev. 1 56 Freescale Semiconductor
Package Description
5.2.2
VR Package Dimensions
Figure 18 provides the mechanical dimensions and bottom surface nomenclature of the 516 PBGA package.
Figure 18. Mechanical Dimensions and Bottom Surface Nomenclature--516 PBGA
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 57
Ordering Information
6
Ordering Information
Figure 19 provides an example of the Freescale part numbering nomenclature for the MPC8250. In addition to the processor frequency, the part numbering scheme also consists of a part modifier that indicates any enhancement(s) in the part from the original production design. Each part number also contains a revision code that refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. For more information, contact your local Freescale sales office.
MPC 8250 A C ZU XXX X
Product Code Device Number Die Revision Level
Process Technology (A = 0.25 micron) Temperature Range (Blank = 0 to 105 C C = -40 to 105 C)
Processor Frequency (CPU/CPM/Bus) Package ZU = 480 TBGA VR = 516 PBGA
Figure 19. Freescale Part Number Key
7
Document Revision History
Table 23. Document Revision History
Revision 0 0.1 Date 11/2001 Initial version 2/2002 * Note 2 for Table 4 (changes in italics): "...greater than or equal to 266 MHz, 200 MHz CPM..." * Table 18: core and bus frequency values for the following ranges of MODCK_HMODCK: 0011_000 to 0011_100 and 1011_000 to 1011_1000 * Table 19: footnotes added to pins at AE11, AF25, U5, and V4. * Table 19: modified notes to pins AE11 and AF25. * Table 19: added note to pins AA1 and AG4 (Therm0 and Therm1). * Table 19: modified note to pin AF25. * * * * * Table 2: Notes 2 and 3 Addition of note on page 8:VDDH and VDD tracking Table 14: Note 3 Table 16: Note 1 Table 18: Note 3 Substantive Changes
Table 23 provides a revision history for this template.
0.2 0.3 0.4
3/2202 3/2002 5/2002
0.5 0.6 0.7 0.8
9/2002
Addition of VR (516 PBGA) package information. Refer to sections 2.2, 4.2, and 5.
10/2002 Table 21, "VR Pinout": corrected ball assignment for the following pins--A12-A17, TA, PD5, PC2. 10/2002 Table 21, "VR Pinout": Addition of L3 to the Core (VDDx) pin list (page 53) 11/2002 Table 21, "VR Pinout": Addition of C18 to the Ground (GND) pin list (page 53)
MPC8250 Hardware Specifications, Rev. 1 58 Freescale Semiconductor
Document Revision History
Table 23. Document Revision History (continued)
Revision 0.9 Date 8/2003 * * * * * * * * * * * Substantive Changes Table 2: Modification to supply voltage ranges reflected in notes 2, 3, and 4 Addition of VCCSYN to "Note: Core, PLL, and I/O Supply Voltages" following Table 2 Addition of Figure 2 Addition of note 1 to Table 3 Table 4: Changes to JA. Addition of JB and JC Table 7, Figure 8: Addition of sp42a/sp43a Figure 3 through Figure 8: Addition of notes or modifications Table 9: Change to sp10 Table 14, Table 16, and Table 18: Removal of PLL bypass mode from clock tables Table 19 and Table 21: Addition of note 1 Addition of SPICLK to PC19 in Table 19 and Table 21. It is documented correctly in the MPC8260 PowerQUICC IITM Family Reference Manual but had previously been omitted from Table 19 and Table 21.
1
3/29/2005 Document template update
MPC8250 Hardware Specifications, Rev. 1 Freescale Semiconductor 59
How to Reach Us:
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Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.
(c) Freescale Semiconductor, Inc., 2003, 2005.
Document Number: MPC8250EC Rev. 1 03/2005

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